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PSMN2R0-30YL
N-channel TrenchMOS logic level FET
Rev. 03 -- 7 January 2010 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in industrial and communications applications.
1.2 Features and benefits
High efficiency due to low switching and conduction losses Suitable for logic level gate drive sources
1.3 Applications
Class-D amplifiers DC-to-DC converters Motor control Server power supplies
1.4 Quick reference data
Table 1. VDS ID Ptot Quick reference Conditions Tmb = 25 C; VGS = 10 V; see Figure 1 and 3 Tmb = 25 C; see Figure 2
[1]
Symbol Parameter drain current total power dissipation gate-drain charge
Min -
Typ -
Max 30 100 97
Unit V A W
drain-source voltage Tj 25 C; Tj 175 C
Dynamic characteristics QGD VGS = 4.5 V; ID = 10 A; VDS = 12 V; see Figure 14 and 15 VGS = 4.5 V; ID = 10 A; VDS = 12 V; see Figure 14 VGS = 10 V; ID = 15 A; Tj = 25 C 7.5 nC
QG(tot)
total gate charge
-
30
-
nC
Static characteristics RDSon drain-source on-state resistance 1.55 2 m
[1]
Continuous current is limited by package.
NXP Semiconductors
PSMN2R0-30YL
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pin 1 2 3 4 mb S S S G D Pinning information Symbol Description source source source gate mounting base; connected to drain
mbb076
Simplified outline
mb
Graphic symbol
D
G S
1234
SOT669 (LFPAK)
3. Ordering information
Table 3. Ordering information Package Name PSMN2R0-30YL LFPAK Description plastic single-ended surface-mounted package (LFPAK); 4 leads Version SOT669 Type number
4. Limiting values
Table 4. Symbol VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM EDS(AL)S Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tmb = 25 C; tp 10 s; pulsed; Tmb = 25 C
[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions Tj 25 C; Tj 175 C Tj 25 C; Tj 175 C; RGS = 20 k VGS = 10 V; Tmb = 100 C; see Figure 1 VGS = 10 V; Tmb = 25 C; see Figure 1 and 3 tp 10 s; pulsed; Tmb = 25 C; see Figure 3 Tmb = 25 C; see Figure 2
[1] [1]
Min -20 -55 -55 -
Max 30 30 20 100 100 667 97 175 175 100 667 151
Unit V V V A A A W C C A A mJ
Source-drain diode
Avalanche ruggedness non-repetitive VGS = 10 V; Tj(init) = 25 C; ID = 100 A; Vsup 30 V; drain-source avalanche RGS = 50 ; unclamped energy
[1]
Continuous current is limited by package.
PSMN2R0-30YL_3
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2010
2 of 14
NXP Semiconductors
PSMN2R0-30YL
N-channel TrenchMOS logic level FET
120 ID (A) 100 (1)
003aac471
120 Pder (%) 80
03aa16
80
60
40
40
20
0 0 50 100 150 200 Tmb (C)
0 0 50 100 150 Tmb (C) 200
Fig 1.
Continuous drain current as a function of mounting base temperature
Fig 2.
Normalized total power dissipation as a function of mounting base temperature
003aac529
103 ID (A) 102
(1)
10 s Limit RDSon = VDS / ID
100 s
10
DC
1 ms
10 ms 100 ms 1 10-1 1 10 102
VDS (V)
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN2R0-30YL_3
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2010
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NXP Semiconductors
PSMN2R0-30YL
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5. Symbol Rth(j-mb) Thermal characteristics Parameter thermal resistance from junction to mounting base Conditions see Figure 4 Min Typ 0.4 Max 1.28 Unit K/W
10 Zth(j-mb) (K/W) 1 = 0.5
003aac481
0.2
10-1
0.1 0.05 0.02
P = tp T
10-2
single shot
tp t T
10-3 10-6 10-5 10-4 10-3 10-2 10-1
tp (s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN2R0-30YL_3
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2010
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NXP Semiconductors
PSMN2R0-30YL
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Symbol V(BR)DSS Characteristics Parameter drain-source breakdown voltage Conditions ID = 250 A; VGS = 0 V; Tj = 25 C ID = 20 A; VGS = 0 V; Tj = 25 C; tav = 100 ns ID = 250 A; VGS = 0 V; Tj = -55 C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 C; see Figure 11 and 12 ID = 1 mA; VDS = VGS; Tj = 150 C; see Figure 12 ID = 1 mA; VDS = VGS; Tj = -55 C; see Figure 12 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 30 V; VGS = 0 V; Tj = 25 C VDS = 30 V; VGS = 0 V; Tj = 150 C VGS = 16 V; VDS = 0 V; Tj = 25 C VGS = -16 V; VDS = 0 V; Tj = 25 C VGS = 4.5 V; ID = 15 A; Tj = 25 C VGS = 10 V; ID = 15 A; Tj = 150 C; see Figure 13 VGS = 10 V; ID = 15 A; Tj = 25 C RG QG(tot) gate resistance total gate charge f = 1 MHz ID = 10 A; VDS = 12 V; VGS = 10 V; see Figure 14 and 15 ID = 0 A; VDS = 0 V; VGS = 10 V ID = 10 A; VDS = 12 V; VGS = 4.5 V; see Figure 14 QGS QGS(th) QGS(th-pl) QGD VGS(pl) Ciss Coss Crss td(on) tr td(off) tf
PSMN2R0-30YL_3
Min 30 35 27 1.3 0.65 -
Typ 1.7 2.13 1.55 0.75 64 59 30 9.8 6.6 3.2 7.5 2.34 3980 857 347 39 65 63 28
Max 2.15 2.45 1 100 100 100 2.63 3.3 2 1.5 -
Unit V V V V V V A A nA nA m m m nC nC nC nC nC nC nC V pF pF pF ns ns ns ns
Static characteristics
Dynamic characteristics
gate-source charge pre-threshold gate-source charge post-threshold gate-source charge gate-drain charge gate-source plateau voltage input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time
ID = 10 A; VDS = 12 V; VGS = 4.5 V; see Figure 14 and 15
VDS = 12 V; see Figure 14 and 15 VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 16
-
VDS = 12 V; RL = 0.5 ; VGS = 4.5 V; RG(ext) = 4.7
-
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2010
5 of 14
NXP Semiconductors
PSMN2R0-30YL
N-channel TrenchMOS logic level FET
Table 6. Symbol VSD trr Qr
[1]
Characteristics ...continued Parameter source-drain voltage reverse recovery time recovered charge Conditions IS = 25 A; VGS = 0 V; Tj = 25 C; see Figure 17 IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 20 V Min Typ 0.78 43 49 Max 1.2 Unit V ns nC
Source-drain diode
Tested to JEDEC standards where applicable.
80 ID (A) 60
003aac470
150 10 ID (A) 100 4
003aac474
VGS (V) = 3
40
2.8
50 20 Tj = 150 C 25 C 0 0 1 2 VGS (V) 3 0 0 2 4 6 8
2.6
2.4 2.2 10 VDS (V)
Fig 5.
Transfer characteristics: drain current as a function of gate-source voltage; typical values
7
003aac475
Fig 6.
Output characteristics: drain current as a function of drain-source voltage; typical values
003aac477
RDSon (m) 6
160 gfs (S) 140
5
VGS (V) = 3 V
120
4
100
3 4 2 10 1 0 50 100 ID (A) 150
80
60
40 0 20 40 60 I (A) D 80
Fig 7.
Drain-source on-state resistance as a function of drain current; typical values
Fig 8.
Forward transconductance as a function of drain current; typical values
PSMN2R0-30YL_3
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2010
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NXP Semiconductors
PSMN2R0-30YL
N-channel TrenchMOS logic level FET
8000 C (pF) 6000 Ciss
003aac480
4 RDSon (m) 3.5
003aac476
3
4000
Crss
2.5
2000
2
0 0 2 4 6 8 10 VGS (V)
1.5 2 4 6 8 V (V) 10 GS
Fig 9.
Input and reverse transfer capacitances as a function of gate-source voltage; typical values
003aab271
Fig 10. Drain-source on-state resistance as a function of gate-source voltage; typical values
003a a c337
10-1 ID (A) 10-2 min 10-3 typ
3 VGS (th) (V)
max
2
max typ
10-4
min 1
10-5
10-6 0 1 2 VGS (V) 3
0 -60
0
60
120
Tj (C)
180
Fig 11. Sub-threshold drain current as a function of gate-source voltage
Fig 12. Gate-source threshold voltage as a function of junction temperature
PSMN2R0-30YL_3
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2010
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NXP Semiconductors
PSMN2R0-30YL
N-channel TrenchMOS logic level FET
2 a
03aa27
VDS ID
1.5
VGS(pl) VGS(th) VGS QGS1 QGS2 QGD QG(tot)
003aaa508
1
0.5
QGS
0 -60
0
60
120
Tj (C)
180
Fig 13. Normalized drain-source on-state resistance factor as a function of junction temperature
10 VGS (V) 8 VDS = 12 (V) 6
003aac473
Fig 14. Gate charge waveform definitions
5000 C (pF) 4000 Ciss
003aac478
VDS = 19 (V)
3000
Coss
4
2000
2
1000
Crss
0 0 20 40 60 QG (nC) 80
0 10-1
1
10
VDS (V)
102
Fig 15. Gate-source voltage as a function of gate charge; typical values
Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
PSMN2R0-30YL_3
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2010
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NXP Semiconductors
PSMN2R0-30YL
N-channel TrenchMOS logic level FET
100 IS (A) 80
003aac469
60
40 Tj = 150 C 20 25 C 0 0.0
0.2
0.4
0.6
0.8
1.0 VSD (V)
Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values
PSMN2R0-30YL_3
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2010
9 of 14
NXP Semiconductors
PSMN2R0-30YL
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669
E b2 L1
A c2
A2
C E1 b3
mounting base D1 H D
b4
L2
1
e
2
3
b
1/2
4
wM A c X
e
A A1 C
(A 3)
detail X L yC 0 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A A1 A2 A3 b b2 b3 2.2 2.0 b4 0.9 0.7 c c2 D (1) D1(1) E(1) E1(1) max 5.0 4.8 3.3 3.1 e 1.27 H 6.2 5.8 L 0.85 0.40 L1 1.3 0.8 L2 1.3 0.8 w 0.25 y 0.1 8 0
1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62
0.25 0.30 4.10 4.20 0.19 0.24 3.80
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC MO-235 JEITA EUROPEAN PROJECTION ISSUE DATE 04-10-13 06-03-16
Fig 18. Package outline SOT669 (LFPAK)
PSMN2R0-30YL_3 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2010
10 of 14
NXP Semiconductors
PSMN2R0-30YL
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history Release date 20100107 Data sheet status Product data sheet Product data sheet Preliminary data sheet Change notice Supersedes PSMN2R0-30YL_2 PSMN2R0-30YL_1 Document ID PSMN2R0-30YL_3 Modifications: PSMN2R0-30YL_2 PSMN2R0-30YL_1
*
Various changes to content.
20090105 20080910
PSMN2R0-30YL_3
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2010
11 of 14
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PSMN2R0-30YL
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
9.3
Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
PSMN2R0-30YL_3
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2010
12 of 14
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PSMN2R0-30YL
N-channel TrenchMOS logic level FET
customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products -- Unless the data sheet of an NXP Semiconductors product expressly states that the product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PSMN2R0-30YL_3
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2010
13 of 14
NXP Semiconductors
PSMN2R0-30YL
N-channel TrenchMOS logic level FET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Contact information. . . . . . . . . . . . . . . . . . . . . .13
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 January 2010 Document identifier: PSMN2R0-30YL_3

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